1. Field of the Invention
The present invention relates to a method for pulling up a defect-free single crystal ingot by the Czochralski method (hereinafter referred to as CZ method).
2. Description of the Related Art
Along with the ultrafine configuration of recent semiconductor integrated circuit, as the factors to decrease the process yield of devices, there are known a Crystal Originated Particle (hereinafter referred to as COP), a fine defect of an oxygen precipitate that becomes the core of Oxidation induced Stacking Fault (hereinafter referred to as OSF), and the presence of Interstitial-type Large Dislocation (hereinafter referred to as L/D).
The COP is a pit that occurs on a wafer surface when a mirror-polished silicon wafer is cleaned with a compound liquid of ammonia and hydrogen peroxide. When this wafer is measured by use of a particle counter, this pit is detected as a particle. This pit originates from a crystal. The COP becomes the cause to deteriorate electrical characteristics, for example, a Time Dependent dielectric Breakdown (TDDB) of an oxide film, a Time Zero Dielectric Breakdown (TZDB) and the like. Further, the presence of the COP on a wafer surface causes a bump in a device wiring process, and may cause a breaking of wire. Furthermore, the COP causes a leakage and the like in the element separation portion, and decreases the process yield of products.
The OSF is a defect that comes to the surface in a thermal oxidation process and the like when a fine oxygen precipitate is introduced into a silicon single crystal at crystal growth, and a semiconductor device is manufactured. This OSF becomes a cause of failures such as the increase of leak current of device and the like. The L/D is also called a dislocation cluster, or a dislocation pit because the L/D causes a pit when a silicon wafer having this defect is dipped into a selective etching liquid composed mainly of fluorinated acid. This L/D becomes a cause to deteriorate electrical characteristics, for example, a leak characteristic, an isolation characteristic and the like. From the above, it is necessary to reduce the COP, the OSF, and the L/D in a silicon wafer used for manufacturing semiconductor integrated circuits.
A method for manufacturing a defect-free silicon single crystal wafer not including these COP, OSF and L/D has been disclosed (for example, refer to Patent Document 1). In this method for manufacturing a defect-free silicon single crystal wafer, there is a step wherein an ingot is pulled up in the axial direction from a silicon melt in a hot zone furnace, in a high pulling velocity profile enough to prevent interstitial lumps (agglomerate of interstitial silicon type point defects), and in a low pulling velocity profile enough to limit vacancy lumps (agglomerate of vacancy type point defects) within a vacancy rich area along the axial direction of the ingot. For this reason, when the pulling velocity of the ingot is defined as V (mm/min), and the axial temperature gradient at the vicinity of the solid-liquid interface of the silicon melt and the ingot is defined as G (° C./mm), by controlling V/G precisely, from a single ingot, a plurality of wafers composed of defect-free areas without the agglomerate of vacancy type point defects and the agglomerate of interstitial silicon type point defects can be manufactured.
From the above, it is known that a defect-free ingot is manufactured in the range of V/G (mm2/min·° C.) in the area where the OSF (P band) that occurs in a ring shape when a thermal oxidation process is performed disappears, and there occurs no L/D (B band). In order to improve the productivity and yield and the like of this defect-free ingot, it is necessary to expand the width of the ingot pulling velocity, i.e., a pure margin for making a defect-free area in the pulling direction and radial direction of the ingot. It is considered that the pure margin has some correlativity with the solid-liquid interface shape at the moment when the ingot is pulled up.
Accordingly, a method for using the solid-liquid interface shape as the control factor for manufacturing a defect-free ingot has been studied, and a method for manufacturing a defect-free ingot in consideration of the shape of the solid-liquid interface of a silicon melt and a silicon single crystal ingot (for example, refer to Patent Document 2) has been disclosed. In this method for manufacturing a defect-free ingot, by appropriately adjusting the relation between the shape of the solid-liquid interface as the border of a silicon melt and a silicon single crystal ingot, and the temperature distribution at the side surface of the ingot during pulling, a defect-free ingot can be manufactured stably with excellent reproducibility.
Patent Document 1: Japanese Unexamined Patent Application Publication No. H11-1393 official gazette corresponding to U.S. Pat. No. 6,045,610 (claim 1, paragraph [0116])
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2001-261495 official gazette (claim 1, paragraph [0148])
However, in the method for manufacturing a defect-free silicon single crystal wafer disclosed in the Patent Document 1 and the method for manufacturing a defect-free ingot disclosed in the Patent Document 2, the change of the axial temperature gradient G arising from the deterioration of furnace inside components of a single crystal puller such as a heater and the like is not taken into consideration, and accordingly, as an ingot is pulled up, defective portions increase inside of the ingot, which has been a problem. In concrete, because the heater becomes thin gradually while the ingot is pulled up, although the heating value per unit area of the heater increases and the axial temperature gradient G decreases gradually, in the manufacturing methods disclosed in the above prior-art Patent Documents 1 and 2, the ingot pulling velocity V is not controlled so as to decrease gradually, the V/G changes, and as one ingot is pulled up, defective portions gradually increase in the inside of the ingot.
Further, in the manufacturing methods disclosed in the above prior-art Patent Documents 1 and 2, it takes much time equivalent to the pulling time for several to several ten ingots by a single puller, to slice an ingot pulled up by the puller and manufacture wafers, and to inspect and confirm the quality of the wafers by observation and measurement, and so, if the ingots are left for this period without adjusting the ingot pulling velocity V in consideration of the change of the axial temperature gradient G arising from the deterioration of the furnace inside components, the yield of defect-free ingots gradually declines as the number of ingots pulled up increases, which has been another problem with the prior art.